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Sourced a higher-res 13-01 image

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Fixes #18
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James Gregory 2019-08-13 22:40:21 +10:00
commit 264f0b2624
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src/chapter-13.md
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@ -107,7 +107,7 @@ from the use of DI to address memory (remember, the loop is unrolled, so
the last instruction is followed by the first instruction), but because
the intervening instruction takes two cycles, there's no penalty at all.
![**Figure 13.1**  *Cycle-eaters in the original WC.*](images/13-01.jpg)
![**Figure 13.1**  *Cycle-eaters in the original WC.*](images/13-01.png)
> ![](images/i.jpg)
> Remember, pipeline penalties diminish with increasing number of cycles,