Normal quotes

27-01.md

@@ -10,7 +10,7 @@ Chapter 27\
 
 In the last chapter, we learned about the markedly peculiar write mode 3
 of the VGA, after having spent three chapters learning the ins and outs
-of the VGA’s data path in write mode 0, touching on write mode 1 as well
+of the VGA's data path in write mode 0, touching on write mode 1 as well
 in Chapter 23. In all, the VGA supports four write modes—write modes 0,
 1, 2, and 3—and read modes 0 and 1 as well. Which leaves two burning
 questions: What is write mode 2, and how the heck do you *read* VGA
@@ -21,13 +21,13 @@ particularly if you followed the description of set/reset in Chapter 25.
 Reading VGA memory, on the other hand, can be stranger than you could
 ever imagine.
 
-Let’s start with the easy stuff, write mode 2, and save the read modes
+Let's start with the easy stuff, write mode 2, and save the read modes
 for the next chapter.
 
 ### Write Mode 2 and Set/Reset {#Heading3}
 
-Remember how set/reset works? Good, because that’s pretty much how write
-mode 2 works. (You *don’t* remember? Well, I’ll provide a brief
+Remember how set/reset works? Good, because that's pretty much how write
+mode 2 works. (You *don't* remember? Well, I'll provide a brief
 refresher, but I suggest that you go back through Chapters 23 through 25
 and come up to speed on the VGA.)
 
@@ -56,12 +56,12 @@ CPU-side input); likewise, bit 1 of the CPU byte is expanded to a byte
 for plane 1, bit 2 is expanded for plane 2, and bit 3 is expanded for
 plane 3.
 
-It’s possible that you understand write mode 2 thoroughly at this point;
+It's possible that you understand write mode 2 thoroughly at this point;
 nonetheless, I suspect that some additional explanation of an admittedly
-non-obvious mode wouldn’t hurt. Let’s follow the CPU byte through the
+non-obvious mode wouldn't hurt. Let's follow the CPU byte through the
 VGA in write mode 2, step by step.
 
-#### A Byte’s Progress in Write Mode 2 {#Heading4}
+#### A Byte's Progress in Write Mode 2 {#Heading4}
 
 Figure 27.1 shows the write mode 2 data path. The CPU byte comes into
 the VGA and is split into four separate bits, one for each plane. Bits
@@ -74,12 +74,12 @@ the CPU byte remains unused in write mode 2 to this day.
 
 The bit of the CPU byte sent to each plane is expanded to a 0 or 0FFH
 byte, depending on whether the bit is 0 or 1, respectively. The byte for
-each plane then becomes the CPU-side input to the respective plane’s
+each plane then becomes the CPU-side input to the respective plane's
 ALU. From this point on, the write mode 2 data path is identical to the
 write mode 0 data path. As discussed in earlier articles, the latch byte
 for each plane is the other ALU input, and the ALU either ANDs, ORs, or
 XORs the two bytes together or simply passes the CPU-side byte through.
-The byte generated by each plane’s ALU then goes through the bit mask
+The byte generated by each plane's ALU then goes through the bit mask
 circuitry, which selects on a bit-by-bit basis between the ALU byte and
 the latch byte. Finally, the byte from the bit mask circuitry for each
 plane is written to that plane if the corresponding bit in the Map Mask
@@ -89,7 +89,7 @@ register is set to 1.
  **Figure 27.1**  *VGA data flow in write mode 2.*
 
   ------------------- -------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
-  ![](images/i.jpg)   *It’s worth noting two differences between write mode 2 and write mode 0, the standard write mode of the VGA. First, rotation of the CPU data byte does not take place in write mode 2. Second, the Set/Reset and Enable Set/Reset registers have no effect in write mode 2.*
+  ![](images/i.jpg)   *It's worth noting two differences between write mode 2 and write mode 0, the standard write mode of the VGA. First, rotation of the CPU data byte does not take place in write mode 2. Second, the Set/Reset and Enable Set/Reset registers have no effect in write mode 2.*
   ------------------- -------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
 
 Now that we understand the mechanics of write mode 2, we can step back
@@ -98,10 +98,10 @@ byte as a single pixel in one of 16 colors. Next imagine that nibble
 turned sideways and written across the four planes, one bit to a plane.
 Finally, expand each of the bits to a byte, as shown in Figure 27.2, so
 that 8 pixels are drawn in the color selected by bits 3-0 of the CPU
-byte. Within the constraints of the VGA’s data paths, that’s exactly
+byte. Within the constraints of the VGA's data paths, that's exactly
 what write mode 2 does.
 
-By “the constraints of the VGA’s data paths,” I mean the ALUs, the bit
+By "the constraints of the VGA's data paths," I mean the ALUs, the bit
 mask, and the map mask. As Figure 27.1 indicates, the ALUs can modify
 the color written by the CPU, the map mask can prevent the CPU from
 altering selected planes, and the bit mask can prevent the CPU from
@@ -113,7 +113,7 @@ These are not really constraints at all, of course, but rather features
 of the VGA; I simply want to make it clear that the use of write mode 2
 to set 8 pixels to a given color is a rather simple special case among
 the many possible ways in which write mode 2 can be used to feed data
-into the VGA’s data path.
+into the VGA's data path.
 
 Write mode 2 is selected by setting bits 1 and 0 of the Graphics Mode
 register (Graphics Controller register 5) to 1 and 0, respectively.