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James Gregory 2013-12-30 18:34:31 +11:00
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@ -12,15 +12,15 @@ This heading refers to the ability of the VGA chip to manipulate up to
four bytes of display memory at once. In particular, the VGA provides
four ALUs (Arithmetic Logic Units) to assist the CPU during display
memory writes, and this hardware is a tremendous resource in the task of
manipulating the VGA’s sizable frame buffer. The ALUs are actually only
manipulating the VGA's sizable frame buffer. The ALUs are actually only
one part of the surprisingly complex data flow architecture of the VGA,
but since they’re involved in almost all memory access operations,
they’re a good place to begin.
but since they're involved in almost all memory access operations,
they're a good place to begin.
### VGA Programming: ALUs and Latches {#Heading3}
I’m going to begin our detailed tour of the VGA at the heart of the flow
of data through the VGA: the four ALUs built into the VGA’s Graphics
I'm going to begin our detailed tour of the VGA at the heart of the flow
of data through the VGA: the four ALUs built into the VGA's Graphics
Controller (GC) circuitry. The ALUs (one for each display memory plane)
are capable of ORing, ANDing, and XORing CPU data and display memory
data together, as well as masking off some or all of the bits in the
@ -42,7 +42,7 @@ performance would slow to a crawl.
Figure 24.1 is a simplified depiction of data flow around the ALUs. Each
ALU has a matching latch, which holds the byte read from the
corresponding plane during the last CPU read from display memory, even
if that particular plane wasn’t the plane that the CPU actually read on
if that particular plane wasn't the plane that the CPU actually read on
the last read access. (Only one byte can be read by the CPU with a
single display memory read; the plane supplying the byte is selected by
the Read Map register. However, the bytes at the specified address in
@ -52,7 +52,7 @@ those four bytes are stored in their respective latches.)
Each ALU logically combines the byte written by the CPU and the byte
stored in the matching latch, according to the settings of bits 3 and 4
of the Data Rotate register (and the Bit Mask register as well, which
I’ll cover next time), and then writes the result to display memory. It
I'll cover next time), and then writes the result to display memory. It
is most important to understand that neither ALU operand comes directly
from display memory. The temptation is to think of the ALUs as combining
CPU data and the contents of the display memory address being written
@ -82,7 +82,7 @@ The latches can also be used to draw a fairly complex area fill pattern,
with a different bit pattern used to fill each plane. The mechanism for
this is as follows: First, generate the desired pattern across all
planes at any display memory address. Generating the pattern requires a
separate write operation for each plane, so that each plane’s byte will
separate write operation for each plane, so that each plane's byte will
be unique. Next, read that memory address to store the pattern in the
latches. The contents of the latches can now be written to memory any
number of times by using either write mode 1 or the bit mask, since they