Normal quotes

21-02.md

@@ -4,7 +4,7 @@
 
 As on the 486, you should keep a careful eye out for AGIs involving the
 stack pointer. Implicit modifiers of ESP, such as **PUSH** and **POP**,
-are special-cased so you don’t have to worry about AGIs. However, if you
+are special-cased so you don't have to worry about AGIs. However, if you
 explicitly modify ESP with this instruction
 
     sub esp,100h
@@ -28,7 +28,7 @@ addressing displacement, such as
 
 suffered a 1-cycle penalty, taking a total of 2 cycles. Such
 instructions take only one cycle on the Pentium, but they cannot pair,
-so they’re still the most expensive sort of **MOV**. Knowing this can
+so they're still the most expensive sort of **MOV**. Knowing this can
 speed up something as simple as zeroing two memory variables, as in
 
     sub eax,eax        ;U-pipe 1
@@ -45,26 +45,26 @@ faster, and six bytes smaller than this sequence:
     mov [MemVar2],0 ;U-pipe 2
 
 Note, however, that my experiments thus far indicate that the two writes
-in the first case don’t actually pair (possibly because the memory
+in the first case don't actually pair (possibly because the memory
 variables have never been read into the internal cache), so you might
 want to insert an instruction between the two **MOV**s—and, of course,
-this is yet another reason why you should always measure your code’s
+this is yet another reason why you should always measure your code's
 actual performance.
 
 ### Register Contention {#Heading4}
 
 Finally, we come to the last major component of superscalar
 optimization: register contention. The basic premise here is simple: You
-can’t use the same register in two inherently sequential ways in a
-single cycle. For example, you can’t execute
+can't use the same register in two inherently sequential ways in a
+single cycle. For example, you can't execute
 
     inc eax     ;U-pipe cycle 1
                 ;V-pipe idle cycle 1
                 ; due to dependency
     and ebx,eax ;U-pipe cycle 2
 
-in a single cycle; **AND EBX,EAX** can’t execute until the value in EAX
-is known, and that can’t happen until **INC EAX** is done. Consequently,
+in a single cycle; **AND EBX,EAX** can't execute until the value in EAX
+is known, and that can't happen until **INC EAX** is done. Consequently,
 the V-pipe idles while **INC EAX** executes in the U-pipe. We saw this
 in the last chapter when we discussed splitting instructions into simple
 instructions, and it is by far the most common sort of register
@@ -131,16 +131,16 @@ pairable U-pipe instruction, as illustrated by this sequence:
        dec ecx       ;U-pipe cycle 2
        jnz LoopTop   ;V-pipe cycle 2
 
-Branches can’t pair in the U-pipe; a branch that executes in the U-pipe
+Branches can't pair in the U-pipe; a branch that executes in the U-pipe
 runs alone, with the V-pipe idle. If a call or jump is correctly
-predicted by the Pentium’s branch prediction circuitry (as discussed in
+predicted by the Pentium's branch prediction circuitry (as discussed in
 the last chapter), it executes in a single cycle, pairing if it runs in
 the V-pipe; if mispredicted, conditional jumps take 4 cycles in the
 U-pipe and 5 cycles in the V-pipe, and mispredicted calls and
 unconditional jumps take 3 cycles in either pipe. Note that **RET**
-can’t pair.
+can't pair.
 
-### Who’s in First? {#Heading6}
+### Who's in First? {#Heading6}
 
 One of the trickiest things about superscalar optimization is that a
 given instruction stream can execute at a different speed depending on
@@ -158,7 +158,7 @@ even though we only added 25 percent more cycles:
        dec ecx           ;V-pipe cycle 2
        jnz LoopTop       ;U-pipe cycle 3
                          ;V-pipe idle cycle 3
-                         ; because JNZ can’t
+                         ; because JNZ can't
                          ; pair in the U-pipe
 
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