Normal quotes

20-02.md

@@ -8,7 +8,7 @@ Any instruction can go through the U-pipe, and, for practical purposes,
 the U-pipe is always executing instructions. (The exceptions are when
 the U-pipe execution unit is waiting for instruction or data bytes after
 a cache miss, and when a U-pipe instruction finishes before a paired
-V-pipe instruction, as I’ll discuss below.) Only the instructions shown
+V-pipe instruction, as I'll discuss below.) Only the instructions shown
 in Table 20.1 can go through the V-pipe. In addition, the V-pipe can
 execute a separate instruction only when one of the instructions listed
 in Table 20.2 is executing in the U-pipe; superscalar execution is not
@@ -26,7 +26,7 @@ finished (that is, once neither the U- nor V-pipe is executing
 anything), the Pentium sends the next instruction through the U-pipe. If
 the instruction after the one in the U-pipe is an instruction the V-pipe
 can handle, if the instruction in the U-pipe is pairable, and if
-register contention doesn’t occur, then the V-pipe starts executing that
+register contention doesn't occur, then the V-pipe starts executing that
 instruction, as shown in Figure 20.2. Otherwise, the second instruction
 waits until the first instruction is done, then executes in the U-pipe,
 possibly pairing with the next instruction in line if all pairing
@@ -70,7 +70,7 @@ conditions are met.
     JMP/CALL near      (1 cycle if predicted correctly;
                         3 cycles otherwise)
 
-    † Can’t execute in V-pipe if address contains a displacement
+    † Can't execute in V-pipe if address contains a displacement
 
 **Table 20.1 Instructions that can execute in the V-pipe.**
 
@@ -131,7 +131,7 @@ in Figure 20.3—a full cycle *faster* than **PUSH [*mem*]**, which takes
 
     ROL/ROR/RCL/RCR  reg,1           (1 cycle)
 
-    †   Can’t pair if address contains a displacement
+    †   Can't pair if address contains a displacement
     †† Includes shift-by-1 forms of instructions
 
 **Table 20.2 Instructions that, when executed in the U-pipe, allow
@@ -141,13 +141,13 @@ V-pipe.**
 * * * * *
 
   ------------------- -------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
-  ![](images/i.jpg)   *A fundamental rule of Pentium optimization is that it pays to break complex instructions into equivalent simple instructions, then shuffle the simple instructions for maximum use of the V-pipe. This is true partly because most of the pairable instructions are simple instructions, and partly because breaking instructions into pieces allows more freedom to rearrange code to avoid the AGIs and register contention I’ll discuss in the next chapter.*
+  ![](images/i.jpg)   *A fundamental rule of Pentium optimization is that it pays to break complex instructions into equivalent simple instructions, then shuffle the simple instructions for maximum use of the V-pipe. This is true partly because most of the pairable instructions are simple instructions, and partly because breaking instructions into pieces allows more freedom to rearrange code to avoid the AGIs and register contention I'll discuss in the next chapter.*
   ------------------- -------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
 
 ![](images/20-02.jpg)\
  **Figure 20.2**  *Instruction flow through the two pipes.*
 
-One downside of this “RISCification” (turning complex instructions into
+One downside of this "RISCification" (turning complex instructions into
 simple, RISC-like ones) of Pentium-optimized code is that it makes for
 substantially larger code. For example,
 
@@ -174,11 +174,11 @@ versus the equivalent:
 
 The single complex instruction takes 3 cycles and is 6 bytes long; with
 proper sequencing, interleaving the simple instructions with other
-instructions that don’t use EDX or **Mem Var**, the three-instruction
+instructions that don't use EDX or **Mem Var**, the three-instruction
 sequence can be reduced to 1.5 cycles, but it is *14* bytes long.
 
   ------------------- ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
-  ![](images/i.jpg)   *It’s not unusual for Pentium optimization to approximately double both performance and code size at the same time. In an important loop, go for performance and ignore the size, but on a program-wide basis, the size bears watching.*
+  ![](images/i.jpg)   *It's not unusual for Pentium optimization to approximately double both performance and code size at the same time. In an important loop, go for performance and ignore the size, but on a program-wide basis, the size bears watching.*
   ------------------- ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
 
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