Normal quotes

13-02.md

@@ -2,7 +2,7 @@
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-“When I looked closely as this, I realized that the two cycles for the
+"When I looked closely as this, I realized that the two cycles for the
 final **ADD** is just the sum of 1 cycle to load the data from memory,
 and 1 cycle to add it to DX, so the code could just as well have been
 written as shown in Listing 13.3. The final breakthrough came when I
@@ -10,7 +10,7 @@ realized that by initializing AX to zero outside the loop, I could
 rearrange it as shown in Listing 13.4 and do the final **ADD DX,AX**
 after the loop. This way there are two single-cycle instructions between
 the first and the fourth line, avoiding all pipeline stalls, for a total
-throughput of two cycles/char.”
+throughput of two cycles/char."
 
 **LISTING 13.3 L13-3.ASM**
 
@@ -27,11 +27,11 @@ throughput of two cycles/char.”
                         ; appropriately for the pair
     mov ax,[bx+8000h]   ;get increments for next time
 
-I’d like to point out two fairly remarkable things. First, the single
+I'd like to point out two fairly remarkable things. First, the single
 cycle that Terje saved in Listing 13.4 sped up his entire word-counting
 engine by 25 percent or more; Listing 13.4 is fully twice as fast as
 Listing 13.1—all the result of nothing more than shifting an instruction
-and splitting another into two operations. Second, Terje’s word-counting
+and splitting another into two operations. Second, Terje's word-counting
 engine can process more than 16 million characters *per second* on a
 486/33.
 
@@ -55,7 +55,7 @@ significant byte first in memory, or *big endian*), like so:
 
 **BSWAP** can also be useful for reversing the order of pixel bits from
 a bitmap so that they can be rotated 32 bits at a time with an
-instruction such as **ROR EAX,1**. Intel’s byte ordering for multiword
+instruction such as **ROR EAX,1**. Intel's byte ordering for multiword
 values (least-significant byte first) loads pixels in the wrong order,
 so far as word rotation is concerned, but **BSWAP** can take care of
 that.
@@ -76,14 +76,14 @@ the obvious conclusion that it would be great if there were some way to
 use the upper and lower 16 bits of selected 386 registers as separate
 16-bit registers, effectively increasing the available register space.
 
-Unfortunately, the x86 instruction set doesn’t provide any way to work
+Unfortunately, the x86 instruction set doesn't provide any way to work
 directly with only the upper half of a 32-bit register. The next best
 solution is to rotate the register to give you access in the lower 16
 bits to the half you need at any particular time, with code along the
 lines of that in Listing 13.5. Having to rotate the 16-bit fields into
-position certainly isn’t as good as having direct access to the upper
-half, but surely it’s better than having to get the values out of
-memory, isn’t it?
+position certainly isn't as good as having direct access to the upper
+half, but surely it's better than having to get the values out of
+memory, isn't it?
 
 **LISTING 13.5 L13-5.ASM**
 
@@ -102,12 +102,12 @@ memory, isn’t it?
 Not necessarily. Shifts and rotates are among the worst performing
 instructions of the 486, taking 2 to 3 cycles to execute. Thus, it takes
 2 cycles to rotate the skip value into CX in Listing 13.5, and 2 more
-cycles to rotate it back to the upper half of ECX. I’d say four cycles
+cycles to rotate it back to the upper half of ECX. I'd say four cycles
 is a pretty steep price to pay, especially considering that a **MOV** to
 or from memory takes only one cycle. Basically, using **ROR** to access
 a 16-bit value in the upper half of a 16-bit register is a pretty
-marginal technique, unless for some reason you can’t access memory at
-all (for example, if you’re using BP as a working register, temporarily
+marginal technique, unless for some reason you can't access memory at
+all (for example, if you're using BP as a working register, temporarily
 making the stack frame inaccessible).
 
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