Normal quotes

11-02.md

@@ -10,12 +10,12 @@ have larger prefetch queues than the 8088 (6 bytes for the 286, 16 bytes
 for the 386) and can perform memory accesses, including instruction
 fetches, in far fewer cycles than the 8088.
 
-However, the prefetch queue cycle-eater *doesn’t* vanish on either the
+However, the prefetch queue cycle-eater *doesn't* vanish on either the
 286 or the 386, for several reasons. For one thing, branching
 instructions still empty the prefetch queue, so instruction fetching
 still slows things down after most branches; when the prefetch queue is
-empty, it doesn’t much matter how big it is. (Even apart from emptying
-the prefetch queue, branches aren’t particularly fast on the 286 or the
+empty, it doesn't much matter how big it is. (Even apart from emptying
+the prefetch queue, branches aren't particularly fast on the 286 or the
 386, at a minimum of seven-plus cycles apiece. Avoid branching whenever
 possible.)
 
@@ -52,8 +52,8 @@ with a 286 is fairly expensive, and memory that can keep up with a 386
 is *very* expensive. Instead, computer designers use alternative memory
 architectures that offer more performance for the dollar—but less
 performance overall—than zero-wait-state memory. (It *is* possible to
-build zero-wait-state systems for the 286 and 386; it’s just so
-expensive that it’s rarely done.)
+build zero-wait-state systems for the 286 and 386; it's just so
+expensive that it's rarely done.)
 
 The IBM AT and true compatibles use one-wait-state memory (some AT
 clones use zero-wait-state memory, but such clones are less common than
@@ -62,7 +62,7 @@ systems—including high-speed caches, interleaved memory, and
 static-column RAM—that insert anywhere from 0 to about 5 wait states
 (and many more if 8 or 16-bit memory expansion cards are used); the
 exact number of wait states inserted at any given time depends on the
-interaction between the code being executed and the memory system it’s
+interaction between the code being executed and the memory system it's
 running on.
 
   ------------------- ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
@@ -70,16 +70,16 @@ running on.
   ------------------- ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
 
 The many memory systems in use make it impossible for us to optimize for
-286/386 computers with the precision that’s possible on the 8088.
+286/386 computers with the precision that's possible on the 8088.
 Instead, we must write code that runs reasonably well under the varying
 conditions found in the 286/386 arena.
 
 The wait states that occur on most accesses to system memory in 286 and
 386 computers mean that nearly every access to system memory—memory in
-the DOS’s normal 640K memory area—is slowed down. (Accesses in computers
+the DOS's normal 640K memory area—is slowed down. (Accesses in computers
 with high-speed caches may be wait-state-free if the desired data is
 already in the cache, but will certainly encounter wait states if the
-data isn’t cached; this phenomenon produces highly variable instruction
+data isn't cached; this phenomenon produces highly variable instruction
 execution times.) While this is our first encounter with system memory
 wait states, we have run into a wait-state cycle-eater before: the
 display adapter cycle-eater, which we discussed along with the other
@@ -104,14 +104,14 @@ Unit.
 And that, my friend, is unmistakably the prefetch queue cycle-eater. I
 might add that the prefetch queue cycle-eater is in rare good form in
 the above example: A 4-to-1 ratio of instruction fetch time to execution
-time is in a class with the best (or worst!) that’s found on the 8088.
+time is in a class with the best (or worst!) that's found on the 8088.
 
-Let’s check out the prefetch queue cycle-eater in action. Listing 11.1
+Let's check out the prefetch queue cycle-eater in action. Listing 11.1
 times **MOV [WordVar],0**. The Zen timer reports that on a
 one-wait-state 10 MHz 286-based AT clone (the computer used for all
 tests in this chapter), Listing 11.1 runs in 1.27 µs per instruction.
-That’s 12.7 cycles per instruction, just as we calculated. (That extra
-seven-tenths of a cycle comes from DRAM refresh, which we’ll get to
+That's 12.7 cycles per instruction, just as we calculated. (That extra
+seven-tenths of a cycle comes from DRAM refresh, which we'll get to
 shortly.)
 
 **LISTING 11.1 L11-1.ASM**
@@ -137,7 +137,7 @@ shortly.)
             call    ZTimerOff
 
 What does this mean? It means that, practically speaking, the 286 as
-used in the AT doesn’t have a 16-bit bus. From a performance
+used in the AT doesn't have a 16-bit bus. From a performance
 perspective, the 286 in an AT has two-thirds of a 16-bit bus (a 10.7-bit
 bus?), since every bus access on an AT takes 50 percent longer than it
 should. A 286 running at 10 MHz *should* be able to access memory at a