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<meta name="vspubdate" content="07/01/97" />
<meta name="vscategory" content="Web and Software Development: Game Development,Web and Software Development: Graphics and Multimedia Development" />
<title>Michael Abrash's Graphics Programming Black Book Special Edition: Yet Another VGA Write Mode</title><!-- HEADER -->
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<title>Michael Abrash's Graphics Programming Black Book Special Edition: Yet Another VGA Write Mode</title>
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<meta name="pages" content="499-504" />
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<p><br /></p>
<h2><a id="Heading1"></a>Chapter 27<br />
<h2 id="Heading1">Chapter 27<br />
Yet Another VGA Write Mode</h2>
<h3><a id="Heading2"></a>Write Mode 2, Chunky Bitmaps,and Text-Graphics Coexistence</h3>
<h3 id="Heading2">Write Mode 2, Chunky Bitmaps,and Text-Graphics Coexistence</h3>
<p>In the last chapter, we learned about the markedly peculiar write mode 3 of the VGA, after having spent three chapters learning the ins and outs of the VGA&rsquo;s data path in write mode 0, touching on write mode 1 as well in Chapter 23. In all, the VGA supports four write modes&mdash;write modes 0, 1, 2, and 3&mdash;and read modes 0 and 1 as well. Which leaves two burning questions: What is write mode 2, and how the heck do you <i>read</i> VGA memory?</p>
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<p>Let&rsquo;s start with the easy stuff, write mode 2, and save the read modes for the next chapter.</p>
<h3><a id="Heading3"></a>Write Mode 2 and Set/Reset</h3>
<h3 id="Heading3">Write Mode 2 and Set/Reset</h3>
<p>Remember how set/reset works? Good, because that&rsquo;s pretty much how write mode 2 works. (You <i>don&rsquo;t</i> remember? Well, I&rsquo;ll provide a brief refresher, but I suggest that you go back through Chapters 23 through 25 and come up to speed on the VGA.)</p>
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<p>It&rsquo;s possible that you understand write mode 2 thoroughly at this point; nonetheless, I suspect that some additional explanation of an admittedly non-obvious mode wouldn&rsquo;t hurt. Let&rsquo;s follow the CPU byte through the VGA in write mode 2, step by step.</p>
<h4 align="left"><a id="Heading4"></a>A Byte&rsquo;s Progress in Write Mode 2</h4>
<h4 align="left" id="Heading4">A Byte&rsquo;s Progress in Write Mode 2</h4>
<p>Figure 27.1 shows the write mode 2 data path. The CPU byte comes into the VGA and is split into four separate bits, one for each plane. Bits 7-4 of the CPU byte vanish into the bit bucket, never to be heard from again. Speculation long held that those 4 unused bits indicated that IBM would someday come out with an 8-plane adapter that supported 256 colors. When IBM did finally come out with a 256-color mode (mode 13H of the VGA), it turned out not to be planar at all, and the upper nibble of the CPU byte remains unused in write mode 2 to this day.</p>
<p>The bit of the CPU byte sent to each plane is expanded to a 0 or 0FFH byte, depending on whether the bit is 0 or 1, respectively. The byte for each plane then becomes the CPU-side input to the respective plane&rsquo;s ALU. From this point on, the write mode 2 data path is identical to the write mode 0 data path. As discussed in earlier articles, the latch byte for each plane is the other ALU input, and the ALU either ANDs, ORs, or XORs the two bytes together or simply passes the CPU-side byte through. The byte generated by each plane&rsquo;s ALU then goes through the bit mask circuitry, which selects on a bit-by-bit basis between the ALU byte and the latch byte. Finally, the byte from the bit mask circuitry for each plane is written to that plane if the corresponding bit in the Map Mask register is set to 1.</p>
<p><a id="Fig1"><!-- </A><A HREF="javascript:displayWindow('images/27-01.jpg',409,401 )"> --><img src="images/27-01.jpg" /><br />
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<BR><A HREF="javascript:displayWindow('images/27-01.jpg',409,401)"> --><b>Figure 27.1</b></a>&nbsp;&nbsp;<i>VGA data flow in write mode 2.</i></p>
<p><a id="Fig1"><img src="images/27-01.jpg" /><br />
<b>Figure 27.1</b></a>&nbsp;&nbsp;<i>VGA data flow in write mode 2.</i></p>
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Graphics Programming Black Book &copy; 2001 Michael Abrash
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