Strip comments and inline ids onto h*
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James Gregory
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362 changed files with 2519 additions and 6694 deletions
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20-02.html
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20-02.html
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@ -10,16 +10,9 @@
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<meta name="vspubdate" content="07/01/97" />
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<meta name="vscategory" content="Web and Software Development: Game Development,Web and Software Development: Graphics and Multimedia Development" />
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<title>Michael Abrash's Graphics Programming Black Book Special Edition: Pentium Rules</title><!-- HEADER -->
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<!-- Empty Reference Subhead -->
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<!--ISBN=1576101746//-->
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<!--TITLE=Michael Abrash's Graphics Programming Black Book Special Edition//-->
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<!--AUTHOR=Michael Abrash//-->
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<!--PUBLISHER=The Coriolis Group, Inc.//-->
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<title>Michael Abrash's Graphics Programming Black Book Special Edition: Pentium Rules</title>
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<meta name="chapter" content="20" />
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<meta name="pages" content="386-390" />
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<!--UNASSIGNED1//-->
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<!--UNASSIGNED2//-->
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</head>
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<body>
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@ -37,13 +30,12 @@
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<p><br /></p>
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<h3><a id="Heading4"></a>V-Pipe-Capable Instructions</h3>
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<h3 id="Heading4">V-Pipe-Capable Instructions</h3>
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<p>Any instruction can go through the U-pipe, and, for practical purposes, the U-pipe is always executing instructions. (The exceptions are when the U-pipe execution unit is waiting for instruction or data bytes after a cache miss, and when a U-pipe instruction finishes before a paired V-pipe instruction, as I’ll discuss below.) Only the instructions shown in Table 20.1 can go through the V-pipe. In addition, the V-pipe can execute a separate instruction only when one of the instructions listed in Table 20.2 is executing in the U-pipe; superscalar execution is not possible while any instruction not listed in Table 20.2 is executing in the U-pipe. So, for example, if you use <b>SHR EDX,CL</b>, which takes 4 cycles to execute, no other instructions can execute during those 4 cycles; if, on the other hand, you use <b>SHR EDX,10</b>, it will take 1 cycle to execute in the U-pipe, and another instruction can potentially execute concurrently in the V-pipe. (As you can see, similar instruction sequences can have vastly different performance characteristics on the Pentium.)</p>
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<p>Basically, after the current instruction or pair of instructions is finished (that is, once neither the U- nor V-pipe is executing anything), the Pentium sends the next instruction through the U-pipe. If the instruction after the one in the U-pipe is an instruction the V-pipe can handle, if the instruction in the U-pipe is pairable, and if register contention doesn’t occur, then the V-pipe starts executing that instruction, as shown in Figure 20.2. Otherwise, the second instruction waits until the first instruction is done, then executes in the U-pipe, possibly pairing with the next instruction in line if all pairing conditions are met.</p>
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<hr />
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<!-- CODE //-->
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<pre>
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MOV reg,reg (1 cycle)
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mem,reg (1 cycle)
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@ -82,7 +74,7 @@ JMP/CALL near (1 cycle if predicted correctly;
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3 cycles otherwise)
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<sup>†</sup> Can’t execute in V-pipe if address contains a displacement
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</pre><!-- END CODE //-->
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</pre>
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<p><b>Table 20.1 Instructions that can execute in the V-pipe.</b></p>
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<hr />
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@ -91,7 +83,6 @@ JMP/CALL near (1 cycle if predicted correctly;
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<p>Besides, almost all operations can be performed by combinations of pairable instructions. For example, <b>PUSH [<i>mem</i>]</b> is not on either list, but both <b>MOV <i>reg</i>,[<i>mem</i>]</b> and <b>PUSH <i>reg</i></b> are, and those two instructions can be used to push a value stored in memory. In fact, given the proper instruction stream, the discrete instructions can perform this operation effectively in just 1 cycle (taking one-half of each of 2 cycles, for 2*0.5 = 1 cycle total execution time), as shown in Figure 20.3—a full cycle <i>faster</i> than <b>PUSH [<i>mem</i>]</b>, which takes 2 cycles.</p>
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<hr />
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<!-- CODE //-->
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<pre>
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MOV reg,reg (1 cycle)
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mem,reg (1 cycle)
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@ -128,7 +119,7 @@ ROL/ROR/RCL/RCR reg,1 (1 cycle)
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<sup>†</sup> Can’t pair if address contains a displacement
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<sup>††</sup> Includes shift-by-1 forms of instructions
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</pre><!-- END CODE //-->
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</pre>
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<p><b>Table 20.2 Instructions that, when executed in the U-pipe, allow V-pipe-executable instructions to execute simultaneously (pair) in the V-pipe.</b></p>
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<hr />
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@ -141,36 +132,34 @@ ROL/ROR/RCL/RCR reg,1 (1 cycle)
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</tr>
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</table>
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<p><a id="Fig2"><!-- </A><A HREF="javascript:displayWindow('images/20-02.jpg',405,144 )"> --><img src="images/20-02.jpg" /><br />
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<!-- </A>
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<BR><A HREF="javascript:displayWindow('images/20-02.jpg',405,144)"> --><b>Figure 20.2</b></a> <i>Instruction flow through the two pipes.</i></p>
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<p><a id="Fig2"><img src="images/20-02.jpg" /><br />
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<b>Figure 20.2</b></a> <i>Instruction flow through the two pipes.</i></p>
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<p>One downside of this “RISCification” (turning complex instructions into simple, RISC-like ones) of Pentium-optimized code is that it makes for substantially larger code. For example,</p><!-- CODE SNIP //-->
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<p>One downside of this “RISCification” (turning complex instructions into simple, RISC-like ones) of Pentium-optimized code is that it makes for substantially larger code. For example,</p>
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<pre>
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push dword ptr [esi]
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</pre><!-- END CODE SNIP //-->
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</pre>
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<p>is one byte smaller than this sequence:</p><!-- CODE SNIP //-->
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<p>is one byte smaller than this sequence:</p>
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<pre>
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mov eax,[esi]
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push eax
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</pre><!-- END CODE SNIP //-->
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</pre>
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<p><a id="Fig3"><!-- </A><A HREF="javascript:displayWindow('images/20-03.jpg',409,210 )"> --><img src="images/20-03.jpg" /><br />
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<!-- </A>
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<BR><A HREF="javascript:displayWindow('images/20-03.jpg',409,210)"> --><b>Figure 20.3</b></a> <i>Pushing a value from memory effectively in one cycle.</i></p>
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<p><a id="Fig3"><img src="images/20-03.jpg" /><br />
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<b>Figure 20.3</b></a> <i>Pushing a value from memory effectively in one cycle.</i></p>
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<p>A more telling example is the following</p><!-- CODE SNIP //-->
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<p>A more telling example is the following</p>
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<pre>
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add [MemVar],eax
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</pre><!-- END CODE SNIP //-->
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</pre>
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<p>versus the equivalent:</p><!-- CODE SNIP //-->
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<p>versus the equivalent:</p>
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<pre>
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mov edx,[MemVar]
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add edx,eax
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mov [MemVar],edx
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</pre><!-- END CODE SNIP //-->
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</pre>
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<p>The single complex instruction takes 3 cycles and is 6 bytes long; with proper sequencing, interleaving the simple instructions with other instructions that don’t use EDX or <b>Mem Var</b>, the three-instruction sequence can be reduced to 1.5 cycles, but it is <i>14</i> bytes long.</p>
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@ -199,10 +188,6 @@ mov [MemVar],edx
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<div align="center">
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Graphics Programming Black Book © 2001 Michael Abrash
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</div><!-- all of the reference materials (books) have the footer and subfoot reveresed -->
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<!-- reference_subfoot = footer -->
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<!-- reference_footer = subfoot -->
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<!-- BEGIN SUB FOOTER -->
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<!-- END FOOTER -->
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</div>
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</body>
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</html>
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